The AS6UA5128 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 524,288 words × 8 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA , t RC , tWC ) of 55/70ns are ideal for low-power applications. Active high and low chip selects (CS) permit easy memory expansion with multiple-bank memory systems.
When CS is high, the device enters standby mode: the AS6UA5128 is guaranteed not to exceed 72 μW power consumption at 3.6V and 55 ns; 41 μW at 2.7V and 70 ns; or 28 μW at 2.3V and 100 ns. The device also returns data when VCC is reduced to 1.5V for even lower power consumption.
A write cycle is accomplished by asserting write enable (WE) and chip select (CS) low. Data on the input pins I/O1–I/O8 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), chip select (CS), with write enable (WE) High. The chip drives I/O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 2.3V to 3.6V supply. The device is available in the JEDEC standard 36(48)-ball FBGA package.