The ADSP-21160N SHARC DSP is the second iteration of the ADSP-21160. Built in a 0.18 micron CMOS process, it offers higher performance and lower power consumption than its predecessor, the ADSP-21160M. Easing portabil-ity, the ADSP-21160N is application source code compatible with first generation ADSP-2106x SHARC DSPs in SISD (Single Instruction, Single Data) mode. To take advantage of the processor!ˉs SIMD (Singe Instruction, Multiple Data) capability, some code changes are needed. Like other SHARCs, the ADSP-21160N is a 32-bit processor that is optimized for high performance DSP appli- cations. The ADSP-21160N includes an 95 MHz core, a dual-ported on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal buses to eliminate I/O bottlenecks.
The ADSP-21160N introduces Single-Instruction, Multiple-Data (SIMD) processing. Using two computa- tional units (ADSP-2106x SHARC DSPs have one), the ADSP-21160N can double performance versus the ADSP-2106x on a range of DSP algorithms.
Fabricated in a state of the art, high speed, low power CMOS process, the ADSP-21160N has a 10.5ns instruc- tion cycle time. With its SIMD computational hardware running at 95MHz, the ADSP-21160N can perform 570 million math operations per second.