This single D-type latch is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
While the latch-enable (LE) input is high, the Q output follows the data (D) input. When LE is taken low, the Q output is latched at the logic level set up at the D input.
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OE does not affect the internal operations of the latch. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.