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STMICROELECTRONICS [STMicroelectronics] LOW POWER J-FET DUAL OPERATIONAL AMPLIFIERS

Each ADC includes a front-end analog multiplexer followed by a Sample and Hold (S/H), and an 8-bit flash-like architecture core analog-to-digital converter. The output data is followed by a switchable 1:1 or 1:2 demultiplexer and LVDS output buffers (100Ω).

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