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Parameters
NSC [National Semiconductor] Octal D-Type Latch with TRI-STATE Outputs
Internal VREF Voltage. Decouple to GND with 0.1 µF capacitor. Differential Data Input. CML. Differential Data Input. CML. Differential Slice Level Adjust Input Differential Slice Level Adjust Input Loss of Lock Indicator. LVTTL active high. Crystal Oscillator Crystal Oscillator Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz). Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz). Reference Source Select. 0 = on-chip oscillator with external crystal; 1 = external clock source, LVTTL. Differential Test Data Input Differential Test Data Input Digital Supply Frequency Loop Capacitor Reference Frequency Select (See Table II) LVTTL. Reference Frequency Select (See Table II) LVTTL. Frequency Loop Capacitor Data Rate Select (See Table I) LVTTL. No Connect Output Driver Supply Differential Retimed Data Output. CML. Differential Retimed Data Output. CML. Disable Clock and Data Outputs. Active high. LVTTL. Differential Recovered Clock Output. CML. Differential Recovered Clock Output. CML. Bypass CDR Mode. Active high. LVTTL. Loss of Signal Detect Output. Active high. LVTTL. Enable Test Data Inputs. Active high. LVTTL.
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