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Parameters
IDT [Integrated Device Technology] FAST CMOS OCTAL REGISTERED TRANSCEIVERS

The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. All voltages are absolute referenced to VSS. The VS offset is tested with all supplies bi- ased at 15V differential (Note 2). All input pin (VIN ) and ITRIP are clamped with a 5.2V zener diode and pull-up resistor to VDD

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